Pipelining on a RISC Architecture

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CIS 480 Introduction To Computer Architecture

Question:

Objectives

This project is designed to help students to understand the pipelining on a RISC architecture (MIPS), pipeline hazards, and hazards mitigation techniques including forwarding and stalling. Students will gain programming experience in C.

Goals

Your team of 2 students will build a simulator of a (5-stage pipelined) MIPS in C. This simulator will read a binary executable file containing a sequence of MIPS instructions and simulate their execution in stages in a (pipelined) MIPS processor.

Project 1 is a non-pipelined MIPS.

Project 2 is a pipelined MIPS without the considerations for branch hazard and data forwarding.

Project 3 is a pipelined MIPS including branch hazard and data forwarding.

Due dates for Project 1, 2 and 3 are October 6, November 5 and December 1, respectively.

Specification

Input

Your simulator will read a binary executable file. It is of size 1KB and consists of 512B of data segment followed by 512B of text segment (offset 0x200). Do not try to open this file as it causes an error. You can view a binary file using od command in linux (e.g., od -Ax -t x4 memory.out) or format-hex command in Windows Powershell (e.g., format-hex memory.out). Assume input files do not contain any errors.

Registers

The user can use any of the 32 MIPS registers (0-31). Please note that $0 is read-only and should always contain the value 0. Your simulator will need to include a register file (e.g., an array of 32 integers) that maintains the values of all the 32 registers and updates the registers as the instructions are executed.

Data segment

The data segment is of 512B and the only form of data will be integer numbers (4 bytes long). I.e., there can be at maximum 128 integer data in the data segment. The data will not contain any other form of data such as string (ascii characters) or floating point numbers. When the program sees load or store instructions, the address will resolve to access one of these 128 integer data. Therefore, as execution proceeds, loads (lw) can read from the data segment and stores (sw) can write to the data segment.

Text segment

The text segment is of 512B, i.e., there can be at maximum 128 MIPS instructions because each MIPS instruction is 4 bytes long. However, due to the presence of branches and jumps, some instructions will be executed multiple times. The text segment will only contain the following MIPS instructions.

Instruc-tion

Syntax

MIPS instruction encoding (32 bits)

(R-type)

Opcode(6)

Rs(5)

Rt(5)

Rd(5)

Shamt(5)

Func(6)

ADD

add $1,$2,$3

000000

00000

100000 (=3210)

SUB

sub $1,$2,$3

000000

00000

100010 (=3410)

SLL

sll $1,$2,5

000000

000000 (=0)

SRL

srl $1,$2,5

000000

000010 (=2)

SLT

slt $1,$2,$3

000000

00000

101010 (=4210)

HALT

halt

000000

00000

00000

00000

00000

001100 (=1210)

(I-type)

Opcode(6)

Rs(5)

Rt(5)

Immediate (16)

ADDI

addi $1,$2,45

001000

LW

lw $1,100($2)

100011

SW

sw $1,100($2)

101011

BEQ

beq $1,$2,Label

000100

BNE

bne $1,$2,Label

000101

 

The ‘halt’ instruction indicates the end of the program but note that it is not an actual MIPS instruction.

Note that branch target will be contained in the program. In other words, it does not go beyond the 512B boundary. Since the text segment begins at 0x200, this means the targets will be in the range of 0x200 ~ 0x400.

Please note the use of labels in the branch (beq and bne) instructions. You will need to calculate the branch target based on the following relationship.

Addr(Label) = Addr(branch_instruction) + 4 + immediate(16 bits)*4

Sample input

Consider an input file as follows (binary view; e.g., od -Ax -t x4 or format-hex in Linux and

Windows, respectively):

000000 00000000 00000000 00000001 00000002

000010 00000000 00000000 00000000 00000000

000200 20010008 8c240000 8c250004 00020940

000210 00020942 0043082a 00000000 00000000

000220 00000000 00000000 00000000 00000000

*000400

Note that this file begins with the data segment (512 bytes) followed by the text segment (512 bytes). The data segment contains two non-zero data at location 8 and 12 and the data is 1 and 2, respectively, and the first instruction is “20010008” which indicates an ADDI instruction.

In general, when you execute a program, OS reads the program executable file and loads it into memory. You can assume the 1KB file mentioned above is an executable file and thus is loaded. Therefore, the 512 bytes of data in the data segment is loaded into Memory[0~511]. The two non-zero data can be explained as Memory[8] = 1 and Memory[12] = 2. The 512 bytes of text segment is loaded into Memory[512~1023]. The first instruction, “20010008” (ADDI) is thus at Memory[512].

Output

Your simulator should show the followings for every cycle of program execution until it encounters an HALT instruction.

Clock cycle count and the value of PC

Data memory words (the first 16 only out of 128 words) Registers ($0 ~ $15 only)

For Project 1, your simulator should output as follows. Note that an arrow sign and the instructions on the right is just for your information; you do not have to print this.

Testing

A few sample test binary files will also be provided about a week before the project is due. Make use of the sample executable to help verify your output.

You can test your design using your own programs. The quality of your simulator will be determined by how much and how varied the tests are. For example, testing if the simulator works for BNE for both the equal and not equal cases, and forward and backward branching, and all combinations of these, would get a better grade than just testing for one case of BNE.

CIS 480 Introduction To Computer Architecture

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